1. Field of the Invention
Embodiments of the invention relates to simulation of an Integrated Circuit (IC) chip for testing of test patterns that are created by Automatic Test Pattern Generation (ATPG) for use with scan circuitry within a physical IC chip.
2. Related Art
Electronic devices today contain millions of individual pieces of circuitry or “cells.” To automate the design and fabrication of such devices, Electronic Design Automation (EDA) systems have been developed. An EDA system includes one or more computers programmed, for use by chip designers, to design electronic devices which may include one or more IC chips. An EDA system typically receives one or more high level behavioral descriptions of circuitry to be built into an IC chip (e.g., in Hardware Description Language (HDL) like VHDL, Verilog, etc.) and translates this behavioral description into netlists of various levels of abstraction. A netlist is typically stored in computer readable media within the EDA system and processed and verified using many well known techniques. The EDA system uses the netlist(s) to ultimately produce a physical device layout in a mask form, for use in fabricating a physical IC chip.
A Design For Test (DFT) process may take a design, for example in the form of a netlist, of an IC chip which implements a desired behavior, for example Digital Signal Processing (DSP), and replace one or more flip-flops 11-12 (FIG. 1A) with special cells called “scan cells” 21-22 (FIG. 1B) that are designed to supply test vectors from primary inputs 31 of IC chip 10 (FIG. 1B) to one or more portions 13. Portions 13 of the original IC chip's design typically include combinational logic, which couples flip-flops 11 and 12. During the just-described replacement of flip-flops with scan cells, portions 13 are typically kept unchanged. Such a modified design has two modes of operation, a mission mode which performs an intended function (e.g. DSP) for which IC chip 10 was designed, and a test mode which tests whether circuit elements in IC chip 10 have been properly fabricated.
Typically, a scan cell 21 (FIG. 1B) in such an modified design of IC chip 10 includes a flip-flop 21F that is driven by a multiplexer 21M; multiplexer 21M supplies to a data input (D input) pin of flip-flop 21F, either a signal SI if operated in test mode (during which time a scan enable signal SE is active) and alternatively supplies another signal MI if operated in the mission mode (during which time signal SE is inactive). A signal which is input to flip-flop 21F is shown in FIG. 1B as the multiplexer's output signal MO. During scan design, scan cells 21 and 22 may be identified by a chip designer as being intended to be coupled into a scan chain, which involves creation of a scan path 23 (see FIG. 1B) by coupling scan cells 21 and 22 (e.g. the input pin SI of cell 22 is coupled to the output pin Q of flip-flop 21F in cell 21). Scan path 23 is an alternative to a mission path 13P through portions 13, and a signal from one of these two paths is selected by multiplexer 22M based on its scan enable signal. Chip designer may designate either a common scan enable signal SE or designate different scan enable signals, to operate multiplexers 21M and 22M.
An additional step in developing an IC chip's design involves generating test patterns to be applied to IC chip 10. A computer programmed with ATPG software may analyze one or more representations of the IC design in the form of netlists and may automatically generate test patterns. Such test patterns (also called test vectors) are applied to scan cells in a physical IC chip by a hardware device (called “tester”) to test, for example, whether certain selected portions of circuitry are fabricated correctly.
More specifically, a tester (not shown) tests IC chip 10 by loading one or more test patterns serially into one or more scan cells 21 (also called “input scan cells”) from primary inputs 31 of IC chip 10 during a shifting operation (also called “loading operation”), while activating the scan enable signal. Primary inputs 31 and primary outputs 32 of IC chip 10 are external pins that are accessible from outside of chip 10, e.g. to any tester. After such a shifting operation, the tester may deactivate the scan enable signal, and operate IC chip 10 for one clock cycle with the test patterns applied to portion 13 (in a “test operation”.)
The test operation is followed by one or more cycles of active scan enable signal(s) in another shifting operation (also called “unloading operation”), wherein results of test operation that were latched by output scan cells 22 are shifted to primary outputs 32 of IC chip 10. The current inventors note that during both the loading operation and the unloading operation, the selected portions 13 of circuitry between the source and sink scan cells 21 and 22 continue to operate normally in the prior art, i.e. all gates in these portions are evaluated.
Prior to fabrication of the physical IC chip, the test patterns are typically applied to a gate-level computer model of the IC chip. For example, computer instructions 40 (FIG. 1C) are obtained by converting an IC design that is expressed in a HDL into software source code (e.g. in programming language C or C++) that is either executed (after compilation) or interpreted (without compilation) in a computer. In the illustration of FIG. 1C, computer instructions 40 include three functions, a first function “Evaluate_Flipflop” simulates a signal at the output pin Q of flip-flop 21F in scan cell 21 (FIG. 1B), a second function “propagate” simulates the propagation of this signal through combinational logic 13, via mission path 13P to the MI input pin of scan cell 22. Finally, a third function “Evaluate_Multiplexer” simulates a signal that is supplied by multiplexer 22M to the input pin D of flip-flop 22F. Execution of computer instructions 40 after compilation is faster than interpreted execution, and therefore it is common to compile such software source code into compiled code.
The function “propagate” described in the previous paragraph may or may not simulate a signal's travel on scan path 23, depending on the configuration. For example, flip-flops typically have another output pin, namely the Q-pin (which is in addition to the Q pin) and in some configurations the Q-pin is used in scan chaining, in which case function “propagate” does not to do any additional simulation. In other configurations, the Q-pin is not used, and instead path divergence happens at cell instantiation. In such configurations, the Q-pin may be simulated, to drive a signal on the scan path 23.
Simulation based on compiled code is described in, for example, “Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation” by Michael A. Riepe et al, published by University of Michigan in March 1994, and incorporated by reference herein in its entirety as background. Moreover, some compiled code simulators of the prior art are also described in U.S. Pat. No. 6,223,141 granted to Ashar on Apr. 24, 2001, which patent is also incorporated by reference herein in its entirety as background. Ashar describes speeding up levelized compiled code simulation using netlist transformations. Specifically, delay-independent cycle-based logic simulation of synchronous digital circuits with levelized compiled code simulation substantially increases speed. Sweep, eliminate, and factor reduce the number of literals. Specifically an eliminate function rids a netlist of gates whose presence increases the number of literals, i.e., collapsing these gates into their immediate fanouts reduces the number of literals. Before collapsing a gate into its fanout, the function estimates the size of the new onset. If the estimated size is greater than a preset limit, the collapse is not performed. Most of the literal count reduction is through the eliminate function.
The current inventors believe that compiled code simulators can become unduly slow. Specifically, the number of test patterns required to achieve high fault coverage increases with circuit size. Moreover, deep sub-micron technology challenges existing fault models with the possibility of more failure mechanisms and more defect types. More fault models, in turn, require more test patterns for the same fault coverage and quality level, which increases the time required to simulate the testing of the test patterns. Hence, the current inventors believe there is a need to further improve the speed of compiled code simulation.